This invention relates to methods of manufacturing printed circuit boards, particularly printed circuit boards having substantially coplanar conductive bumps on the surface thereof and to printed circuit boards having solid interconnects between the conductive layers thereof
Standard flexible printed circuit boards comprise a flexible dielectric substrate having circuit lines attached to one or more surfaces thereof. Typically, electrical connections are made between such printed circuit boards and other electrically conductive components by means of conductive bumps which are in electrical communication with the circuit lines. Usually, the conductive bumps are formed by electroless or electrolytically plating the bumps on one or more surfaces of the printed circuit board. The resulting bumps may be polished to provide a plurality of bumps whose top surfaces are intended to be substantially coplanar.
In certain applications it is necessary that the printed circuit boards have a large number of conductive bumps on the surface thereof. Moreover, it is necessary that a large number, if not all, of the bumps extend to essentially the same distance above the surface of the printed circuit board, i.e., that the conductive bumps have substantially coplanar upper surfaces. Unfortunately, the standard methods that are used to form bumps on a printed circuit board do not easily meet these requirements.
Typically, flexible printed circuit boards are fabricated in a continuous roll process to facilitate handling of the thin materials that are used to form such boards. The steps required to fabricate a two conductor layer flexible cable, such as metallizing the dielectric, circuitizing the metal and holemaking can all be performed on flexible substrates in roll form. Although roll processing is suitable for materials that have good mechanical strength and tear resistance, such as polyimides, roll processing is not suitable for Teflon-based materials, which typically have better electrical characteristics than polyimides but poorer mechanical properties. Roll processing is also not suitable for the manufacture of the very thin, low dielectric polymers that typically lack the continuous glass fiber reinforcement of rigid printed circuit boards. Furthermore, roll processing is not readily adaptable to fabricating cables with multiple conductive layers where lamination of additional dielectric layers would be required. Thus, when three or more conductive layers are required in the flexible cable or a circuit board, the required lamination step can be more readily accomplished by employing panel form processing as opposed to continuous roll processing.
In panel form processing the partially completed circuit board is conveyed horizontally on rollers or mounted in a frame for vertical processing. During processing, the circuit board is subjected to stretching which can cause damage, such as tearing or wrinkling of the thin panel. Furthermore, the panels tend to shrink or grow as they go through various thermal excursions, or etching, or plating of copper, or addition of dielectric layers. Since the final product has precise dimensional requirements and requires precise layer to layer alignment, this change in size is problematic. Accordingly, special steps must be taken to prevent damage of flexible cables during fabrication which often offsets the performance advantages of these products with large cost penalties. Thus, panel processing is not well suited to the fabrication of thin flexible cables or thin circuit boards.
In multi-layer printed circuit boards, i.e., circuit boards comprising at least two conductive layers and two dielectric layers, it may be necessary to interconnect the conductive layers on the opposing surfaces of at least one of the dielectric layers. Conventionally, the inter-layer connections between such conductive layers are made by drilling a hole through the conductive layers and the dielectric substrate and plating the resulting via with metal. Since each hole must be drilled individually, this process is time-consuming and expensive. Moreover, the practical minimum size of the holes that are normally produced by such mechanical drilling processes are between 4 to 10 mils. For high performance circuit boards it would be desirable to have hole sizes as small as 2 mils in diameter or even 1 mil.
An alternative approach to forming interconnections between the conductive layers of a multi-layer printed circuit board is to use partial depth or blind vias that are made in the dielectric substrate only. Again the vias are plated to connect the conductive layers that are subsequently formed on opposing surfaces of the substrate. Blind vias can be made by conventional mechanical drilling, or alternatively by laser ablation, by plasma etching, or by photolithography if the dielectric material is photoimageable. Blind vias make more efficient use of space than through vias because additional circuit elements can be included along their axis. Nonetheless, the blind vias can be very difficult to clean and plate because process fluids cannot flow through the smaller hole. As a result, the process fluids tend to get trapped in the vias. Flux and solder also tend to collect in the holes during later processing steps. The accumulation of flux and solder in the vias ultimately can lead to failure of the resulting printed circuit board. For this reason, a variety of methods have been proposed to provide some method of filling the vias after they are plated with various types of materials, both conductive and non-conductive, as a means to provide a planar surface to the printed circuit boards that is not inclined to trap process fluids or materials. However, such hole filling methods tend to add additional processing and material costs to the fabrication of a printed circuit board.
Accordingly, it is desirable to have new methods for forming printed circuit boards, including multi-layer printed circuit boards, that overcome these disadvantages. A method which simultaneously produces a plurality of solid conductive bumps that can be used as interconnectors between the conductive layers on opposing surfaces of a dielectric substrate is desirable. A method that produces a plurality of conductive bumps whose upper surfaces are substantially coplanar is especially desirable A method that provides rigidity and dimensional stability to the flexible or thin printed circuit boards, especially during the early stages of processing, is also desirable.
In accordance with the present invention, a printed circuit board comprising a plurality of conductive bumps whose upper surfaces extend to essentially the same height above the surface of a dielectric substrate is provided. The printed circuit board is made by a process comprising the steps of: forming a substantially planar metallic layer having a first thickness on at least one surface of the dielectric; applying a first photoresist on the metal layer; imaging the first photoresist to define a predetermined pattern of conductive bumps; etching the exposed portions of the metal layer to a second thickness to form the conductive bumps; removing the first photoresist; applying a second photoresist to the metal layer; imaging the second photoresist to define a predetermined pattern of circuitry; etching the exposed portions of the metal layer to provide the electrical circuitry; and removing the second photoresist to provide a printed circuit board having a plurality of conductive bumps that extend to essentially the same height above the surface of the dielectric. Based on the measurements of more than 11,000 conductive bumps formed in accordance with the present invention it has been determined that the coefficient of variation (i.e., the standard deviation divided by the mean) in the height of the bumps above the surface of the substrate is 4% This value corresponds to a bump height coplanarity of +/xe2x88x921.5 microns. Such bumps are hereinafter referred to as xe2x80x9csubstantially coplanar conductive bumps.xe2x80x9d
In a preferred embodiment, the first etching step comprises one or more treatments with an etching agent at a temperature below 110xc2x0 F. The preferred etching agent comprises cupric chloride in an aqueous hydrochloric acid solution. It has been determined that such etching results in less thinning at the base of the conductive bumps than conventional etching processes which typically employ temperatures of greater than 120xc2x0 F. and other etchants.
The present invention also provides a method for preparing printed circuit boards, particularly multi-layer printed circuit boards, wherein two conductive layers that are disposed on opposing sides of a dielectric layer are inter-connected by at least one of the substantially coplanar conductive bumps. The method of forming such multi-layered printed circuit boards comprises the additional steps of depositing a second dielectric layer on the substantially coplanar conductive bumps and circuitry; exposing the upper surface of at least one of the conductive bumps; and depositing a second metal layer on the second dielectric layer and the exposed upper surface of the conductive bump.
The present invention is also related to a method for increasing the rigidity of a multi-layer structure that is used to form a flexible printed circuit board. The method comprises the steps of: applying a metal layer having a first height on at least one surface of a dielectric substrate; applying a first photoresist to the metal layer, imaging the photoresist to provide at least one section of remaining photoresist defining an opening therein and at least one exposed region of the metal layer; etching the exposed region of the metal layer to a second height; and removing the remaining photoresist to provide a multi-layered structure comprising a dielectric layer and a metal layer comprising at least one region having a second height and at least one region having a first height. The region having the second height is the basis for the electrical circuitry that is formed during subsequent manufacturing steps. Preferably, the region having the first height, hereinafter referred to as a xe2x80x9cborderxe2x80x9d, surrounds the region having the second height. The border reinforces the multi-layer structure during subsequent manufacturing steps, thus rendering the multi-layer structure easier to handle.